[PROJECT] CODEC selected by IRS Call for projects (Univ. Grenoble Alpes)

on the April 8, 2019

In the context of IRS call for projects (Initiatives de Recherche Stratégiques) held by the IDEX Univ. Grenoble Alpes, the CODEC project (HW/SW CO-DEsign of processor Countermeasures) has been selected by the MSTIC research department committee and will begin in april 2019 for a duration of 2 years. This project is led by Christophe Deleuze (LCIS Laboratory) and represents a new collaboration between the LCIS Lab and Verimag focused on designing applications resilient against fault injection.

A complementary approach

This project relies on :
  • two laboratories with complementary fields of expertise:
    • the LCIS Lab (Valence) specialized in hardware security (simulation and fault injection, design of hardware countermeasures)
    • the Verimag Lab (Grenoble) specialized in the analysis of software vulnerabilities
  • several PhDs currently in progress in these labs
Its goal is to take advantage of these complementary approaches (while mitigating their limitations) in order to propose a new methodology for analysing vulnerabilities (precision of hardware fault models v. speed of software level analysis, efficiency of hardware countermeasures v. low cost and flexibility of software countermeasures) against state-of-art attacks (multiple faults model).


  • Task 1: Method for the analysis of vulnerabilities based on a multi-layer model (HW/SW)
  • Task 2: Analysis of the criticality of vulnerabilities
  • Task 3: Design of effective countermeasures
  • Task 4: Integration in a toolchain
Therefore, this project will propose a holistic approach for the analysis of embedded applications combining the analysis of both processor and software based on tools developed by the two partners (Secure-RTL for LCIS, Lazart for Verimag). It will also advance research on the the field of countermeasures and the difficulty of assessing their effectiveness against multiple faults.
Published on August 6, 2020